Issue | Title | |
Vol 12, No 2 (2020) | Design and Simulation of Acoustic Data Communication Model for Security Systems | Abstract |
V. Mathiazhagan, J. Mohamed Safeuq, Nikhil Divakaran, Raghul Srinivasan, Nithesh Balaji | ||
Vol 4, No 7 (2012) | Design and Simulation of Boost Converter with Ripple Reduction | Abstract |
M. Bhuvaneswari, K. Dhayalini | ||
Vol 8, No 7 (2016) | Design and Simulation of Five Level Inverter Based DSTATCOM using Space Vector Modulation | Abstract |
K. V. Haris, C. Hrudhya Kurian, P. Anil Antony | ||
Vol 3, No 6 (2011) | Design and Simulation of Serial and Parallel PG-LDPC Decoder | Abstract |
M.M. Vijay, K. Mohaneswari | ||
Vol 8, No 6 (2016) | Design of 4-Bit Ripple Carry Adder Using Modified-GDI Technique | Abstract |
Poonam Dhruwe, Chandrahas Sahu | ||
Vol 2, No 5 (2010) | Design of an Embedded System for Automated Intraocular Pressure Monitoring (with Implementation and Analysis) | Abstract |
Shriram K Vasudevan, S. Karthick, R. Sivaraman | ||
Vol 4, No 2 (2012) | Design of ANSI S1.11 1/3-Octave Filter Bank for Low Power Digital Hearing Aids | Abstract |
D. Tharini, J. Prathishkumar | ||
Vol 5, No 4 (2013) | Design of Bridgeless Buck Converter to Improve the Power Factor | Abstract |
R. Mythili, M. Gomathy, B. Yazhini, D. Madhumitha | ||
Vol 6, No 3 (2014) | Design of Compact Hairpin Structure for Microstrip Bandpass Filter | Abstract |
N. Priyanga, S. Karthie | ||
Vol 10, No 7 (2018) | Design of Differential Input High Gain Op-Amp Using 180 nm Technology | Abstract |
Kiran B. Admane, Dr. M. B. Mali | ||
Vol 5, No 3 (2013) | Design of FFT & IFFT Using Double-Precision Fused Floating Point Operations | Abstract |
T. Tamil Selvi, G. Karthy | ||
Vol 4, No 5 (2012) | Design of Fixed-Width Multiplier using Baugh-Wooley Algorithm | Abstract |
V. Sathya, P. Devasundar | ||
Vol 3, No 5 (2011) | Design of Four Channel Uniform Filter Bank and Oversampled Three Channels FIR Filter Banks for 2-D Image | Abstract |
S.R. Chougule, Dr.R.S. Patil | ||
Vol 10, No 3 (2018) | Design of Fractional Order PID Controller for Integrating Time Delay Systems | Abstract |
Dr. G. Saravanakumar, Alex Babu, Rinoy John, M. Vishnuprasad, Sivaguru Sivaguru | ||
Vol 4, No 4 (2012) | Design of High Accuracy Fixed Width Modified Booth Multiplier for MAC Unit | Abstract |
M. Thamaraiselvi, G.R. Mahendra Babu | ||
Vol 10, No 7 (2018) | Design of High Gain Bandwidth CMOS Operational Amplifier | Abstract |
Deepak Kurwade, Dr. M. B. Mali | ||
Vol 4, No 7 (2012) | Design of Linear Precoder to Maximize Sum Rate Capacity | Abstract |
V. Kejalakshmi, R. Thilagavathy, S. Arivazhagan | ||
Vol 9, No 6 (2017) | Design of Low Power 8 Bit Carry Select Adder Using 14T Transistor 1 Bit Adder | Abstract |
Pooja Chawhan, Akanksha Sinha | ||
Vol 3, No 9 (2011) | Design of Low Power High Performance Parallel-Prefix Adders | Abstract |
K. Saranya | ||
Vol 9, No 6 (2017) | Design of Low Power Multi bit VCO based Quantizer using 90nm Technology | Abstract |
Anjali Jain, Pankaj M. Gulhane | ||
Vol 5, No 6 (2013) | Design of Optimal Baseband Processor for Modernised GPS Signals | Abstract |
S. Mariappan, G. Sasibhusana Rao, Swarna Ravindra Babu | ||
Vol 7, No 6 (2015) | Design of Power Quality Monitoring System Based On Labview | Abstract |
Amit Agrawal, Dheeraj Jaiswal, Dharmendra Kumar, F. Fareeza | ||
Vol 9, No 3 (2017) | Design of Power Reduced Architecture of ECG Based Processor for Predicting Ventricular Arrhythmia | Abstract |
C. Sathya, Dr. T. R. Ganesh Babu, S. Aruna Devi | ||
Vol 4, No 7 (2012) | Design of Radio Frequency Power Amplifier in L-BAND using BJT Device AT - 42070 for Orthogonal Frequency Division Multiplexing | Abstract |
G. Sharmila, E.G. Govindan, V. Mantharachalam | ||
Vol 5, No 8 (2013) | Design of Various PFD and Charge-Pump Architectures for a PLL- a Survey | Abstract |
V. Anoor Dharani, G. Divya, N. Esack, M.Gokul Raj, Dr H. Mangalam, N.K Anushkannan | ||
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ISSN: 0974 – 9594