| Issue | Title | |
| Vol 8, No 8 (2016) | FFT Analysis on Partial Discharge Modeling of Transformer Solid Insulation | Abstract |
| Chilaka Ranga, Ashwani Kumar Chandel | ||
| Vol 9, No 1 (2017) | Financial and Risk Analysis in Data Mining | Abstract |
| S. Janani Priya, P. Sangeethaa | ||
| Vol 2, No 7 (2010) | FIR Digital Differentiator as an Efficient Versatile Multifunction Configuration | Abstract |
| Raj kumar, Jyoti Saxena, Neeraj Gill | ||
| Vol 5, No 4 (2013) | FPGA Based Pipelined Architecture for SPIHT | Abstract |
| S. Soumya Priyadarshni, P. Kavitha | ||
| Vol 4, No 7 (2012) | FPGA Implementation of Digit-Serial Architecture for Various Digit-Size and Wordlength in Viterbi Decoder | Abstract |
| T. Kalavathidevi, K.V. Punitha, Dr. C. Venkatesh | ||
| Vol 2, No 7 (2010) | FPGA Implementation of Floating Point Modules for Evaluating Accurate Arithmetic Expression and DSP Applications | Abstract |
| N. RamyaRani | ||
| Vol 2, No 9 (2010) | Fuzzy Logic PID Control for Automatic Voltage Regulator System | Abstract |
| A. Dominicsavio, P. Poongodi, S. Samuel Ebenezer | ||
| Vol 3, No 3 (2011) | Global Chaos Synchronization of Chen and Cai Systems by Active Nonlinear Control | Abstract |
| Dr.V. Sundarapandian, R. Karthikeyan | ||
| Vol 3, No 3 (2011) | Global Chaos Synchronization of Hyperchaotic Liu and Hyperchaotic Chen Systems by Active Nonlinear Control | Abstract |
| Dr.V. Sundarapandian, R. Karthikeyan | ||
| Vol 3, No 7 (2011) | Global Chaos Synchronization of Li and Pan Chaotic Systems by Active Nonlinear Control | Abstract |
| Dr.V. Sundarapandian | ||
| Vol 3, No 4 (2011) | Global Chaos Synchronization of Liu-Su-Liu and Li Systems by Active Nonlinear Control | Abstract |
| Dr. V. Sundarapandian | ||
| Vol 3, No 3 (2011) | Global Chaos Synchronization of T and Liu-Chen-Liu Systems by Nonlinear Control | Abstract |
| Dr.V. Sundarapandian, R. Suresh | ||
| Vol 3, No 4 (2011) | Gradient Based Optimal Power Flow | Abstract |
| P. Ramachandran, Dr. R. Senthil | ||
| Vol 7, No 6 (2015) | GSM Based Remote Monitoring of Transformer Parameters | Abstract |
| Rahul Ranjan, Supratik Das, Ramesh P. Gupta, Rahul Srivastava, Vikas Kr. Sah, G. Pandisabareeswari | ||
| Vol 7, No 4 (2015) | Hardware Efficient Transceiver Microcell Architecture of USB 2.0 for High Speed data Communication using FPGA | Abstract |
| Zessha Mishra, Anil Kumar Sahu | ||
| Vol 4, No 7 (2012) | Hardware Implementation of Fast Transversal Least Mean Square Algorithm in Acoustics, Speech, and Signal Processing (ASSP) Using TMS320C5X Processor | Abstract |
| J. Jebastine, Dr.B. Sheela Rani | ||
| Vol 3, No 10 (2011) | Harmonics Reduction in Multilevel Inverter Systems | Abstract |
| K. Gaayathry | ||
| Vol 9, No 2 (2017) | Harmonizing Mechanism for Power Saving and Delay Reduction in LTE Networks using DRX | Abstract |
| P. Arunagiri, G. Nagarajan | ||
| Vol 5, No 3 (2013) | HCCB Data Encoding and Decoding Data from Mobile | Abstract |
| R. Kaviarasi, K. Suganya, S. Anitha | ||
| Vol 3, No 6 (2011) | High Level Synthesis of Data Flow Graphs Using Integer Linear Programming | Abstract |
| S. Anbuyazhini, D.S. Harishram | ||
| Vol 2, No 9 (2010) | High Speed Area Efficient VLSI Structure for Real Time Image Computing | Abstract |
| V. P. Abithamol, E.P. Sumesh, R. Vidhyalavanya | ||
| Vol 4, No 5 (2012) | High Speed Low Power Viterbi Decoder using M-Algorithm | Abstract |
| P. Sangeetha, J. Muralidharan | ||
| Vol 2, No 10 (2010) | High Speed Parallel Butterfly Architecture for Computing Circular Convolution Based on FNT Using Modulo 2n+1partial Product Multiplier | Abstract |
| B. Hemalatha, K. Ashok Babu, S. Pothalaiah | ||
| Vol 3, No 1 (2011) | Higher Order Neural Networks Learning by Extended Kalman Filter | Abstract |
| Agya Mishra, R.N. Yadav, D.K. Trivedi | ||
| Vol 9, No 1 (2017) | Human – Computer Interaction | Abstract |
| Dr. G. Satyavathy, M. RachelBlessie | ||
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ISSN: 0974 – 9594