Srividhya, V.
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Vol 2, No 8 (2010) - Articles
Power Optimization for Dual-Clock FIFO with Closedown Able and Reinstate Able Clock Domains
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Vol 1, No 6 (2009) - Articles
Design of Novel Ultra-Low Leakage CMOS Sleepy Stack Structure for circuits with Low Leakage Power Consumption
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Vol 1, No 7 (2009) - Articles
High-Speed 4 BIT Flash ADC Using CMOS Latched Comparator with Current Steering Logic SR Latch
Abstract
ISSN: 0974 – 9624