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High-Speed 4 BIT Flash ADC Using CMOS Latched Comparator with Current Steering Logic SR Latch
Abstract
This paper describes a latched comparator for 4-bti flash DCs. A modified CMOS Latched comparator with Current Steering Logic SR latch is proposed to reduce the delay and improve the speed of operation. Current Steering Logic SR Latch (CSL-SR) architecture is used to achieve high speed of operation, high gain bandwidth, reduced power consumption and less area. The evaluation speed of an amplifier is proportional to the evaluation chain conductivity and is inversely proportional to the capacitance. Since the number of transistors in the evaluation path is less, which eads to less delay and reduced power consumption. Performance results are obtained for an operating frequency of 3GHz in 0. 18μm TSMC technology using Cadence Spectre. The proposed comparator has 66.67% reduction in delay and reduced power consumption by 35. 9% compared to the existing CMOS Latched comparator.
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References
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