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Table of Contents
Articles
| A 30nW Sub-Threshold Adiabatic Carry Look-Ahead Adder in 90nm CMOS |
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| S. Saraswathi, G. K.V. N. Sharada | 85-88 |
| Analysis of Floorplanning Techniques for ASIC Development |
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| Sachin Pandya, Rajendrakumar Patel | 89-95 |
| Design & Analysis of an Area-Efficient, Low-Power 8-bit Multiplier in Modified GDI Cells using the Urdhva-Tiryagbhyam Theorem |
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|
| Bobby Nelson, Ravi Tiwari | 96-103 |
| Review of Multi-Bit Flip Flop Technique |
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|
| Nareshchandra Patel, Mehul L. Patel | 104-109 |
| Design of a Low-Power & Lower-Delay 8-bit SRAM Cell Using Pulsed Latch Circuit in 32nm Technology |
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| N. Namrata, Khemraj Deshmukh | 110-115 |
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ISSN: 0974 – 9624