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Comparative Performance Evaluation of Pattern Matching Algorithm for Intrusion Detection System Uses Memory Utilization

Sunil N. Chavda, Jaykaran Singh, Mukesh Tiwari

Abstract


The increasing rate of data in network compromised security threats and loss of data integrity. The event of network threats is known as intrusion. The detection of intrusion applies in software as well as hardware approach. The process of intrusion detection by hardware approach is very critical issue because the memory utilized is very high due to storage of patterns and regular expressions. In current research trend, various pattern matching algorithms are used such as AC, BM and WM. These algorithms use high storage for memory blocks. The impact of memory generates deficiency in intrusion detection process. In this paper we present the performance evaluation of all these algorithms implemented in FPGA with Xilinx software package for valuation of memory performance. Finally we enlist the comparative memory usage of this entire algorithm.

 


Keywords


Automata, FPGA, Intrusion Detection Systems (IDPs), Intrusion Prevention Systems (IPSs) and Pattern Matching

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References


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