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A High Speed and Area Efficient Floating Point Complex Number Multiplier on FPGA

Jaya Lakshmi Mathala, Pushpa Kotipalli



Area, power dissipation and accuracy are very important factors in VLSI design. But in real time DSP applications high performance is the prime target. Hence there should be a trade-off between those three factors. In this paper we have implemented an IEEE-754 single precision floating point complex number multiplier which uses only three dedicated 24 bit multipliers instead of four multipliers. This 24 bit multiplier makes use of an optimized4x4 multiplier which is high speed .In this paper we have compared our complex number multiplier with another complex number multiplier which makes use of Booth encoded Wallace tree algorithm for 4x4 multiplications. The results are compared and an area of 54.2% was reduced on FPGA .A slack of 2.141 is obtained, which is 100.00 for complex number multiplier using Booth encoded Wallace tree algorithm at 10 MHz .


Booth Encoded Wallace Tree, Complex Number Multiplier, IEEE- 754 Multiplier, Floating Point Adder/Subtractor.

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