Analysis of Floorplanning Techniques for ASIC Development

Abstract

The nature of floorplanning in complex hierarchical designs decides timing closure, power dissipation, interconnect length and area of chip. Particularly Floorplanning includes manual arrangement of hard macros such that area occupied on the silicon will be less and hence less congestion. Most of the problems in VLSI physical design process are Non-Deterministic Polynomial time (NP) hard problems [6]. The future growth of VLSI circuits relies on the development of physical design automation tools [5]. In the physical design process, Floorplanning is an important step, because it sets up the ground work for a good layout. It is the problem of placing a set of circuit modules on a chip to minimize the total area and interconnect cost. Various aspects of VLSI floorplanning problem have been studied in this paper.

The VLSI Design Flow for ASIC comprises of various steps like design specification, architectural design, RTL modeling, synthesis, physical design, layout signoff, fabrication, package and test. The physical design process is further divided into partitioning, floorplanning, placement, clock tree synthesis, signal routing and timing closure. Floorplanning acts as very important activity in physical design because it sets up the ground work for a good layout. The nature of floorplanning in complex hierarchical designs decides timing closure, power dissipation and area of chip and interconnects’ length. In this paper various floorplanning approaches are studied and their relative pros and cons are inferred and reported.