Kumar, Sandeep

• Vol 9, No 4 (2017) - Articles
  A Power Efficient Pulse Triggered Flip-Flop by X-OR Based Clock Gating Scheme at 32nm Technology
  Abstract
• Vol 9, No 6 (2017) - Articles
  A Review on Low Power Design Techniques of Flip-Flop
  Abstract
• Vol 10, No 5 (2018) - Articles
  Design of SISO Shift Register by Using Pulse Triggered Flip-Flop for Effective Area and Power Minimization at 32nm Technology
  Abstract