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Improving the Power Delay Performance of Parallel Prefix Adders
Abstract
Binary adder is the critical element in most digital
circuit designs including digital signal processors (DSP) and
microprocessor data path units. As such, extensive research continues
to be focused on improving the power delay performance of the
adder. In VLSI implementations, parallel-prefix adders are known to
have the best performance.
Parallel-prefix adders are known to have the best performance in
VLSI designs. Due to routing overhead and complexity in logic
blocks it will not directly translate into FPGA implementations. In
this paper there are three types of parallel prefix adders i.e. 1.the
Kogge-Stone, 2.sparse Kogge-Stone, and 3.spanning tree adder and
compares with the simple Ripple Carry Adder, Carry Skip Adder and
carry look ahead adder. These designs of varied adders were
implemented on a Xilinx Spartan 3E FPGA and delay measurements.
In this paper for simulation purpose Model sim is used, and further
synthesizing Xilinx-ISE tool is used.
Keywords
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