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Power Estimation of Switching Activity for Low – Power Implementation on FPGA

Kiritkumar Bhatt, A.I. Trivedi

Abstract


The FPGAs can be configured by the end-user to implement any digital system virtually, which may use millions of gates to be operated at few hundred MHz speed. Because of its reprogrammability, the FPGAs become very popular for the applications where prototyping and economic viability are of great concern. The state-of-the-art fabrication and manufacturing technologies are used to produce the current FPGAs, which comprise of high degree of integration and huge number of transistor count to make it suitable for today’s applications with high performance, but face a power consumption problem. Lower power consumption is a critical design issue in most embedded systems with CMOS technology, where logic switching is a significant factor affecting the system power consumption. The higher the switching frequency the larger the power consumed. This paper discusses the major power consumption sources in VLSI circuit with the primary focus on switching activity, its computation and its power estimation carried out by probabilistic approach.


Keywords


Power Estimation, Probabilistic Approach, Switching Activity, Low Power

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References


A. Papoulis and S. U. Pillai, ”Probability, random variables and stochastic processes” 4th Ed. McGraw – Hill Inc., 2002

K.S.Trivedi, “Probability and statistics with reliability, queuing and computer science applications, New York, Wiley, 2002.

D. Baran, M.Aktan, H. Karimiyan, V.G. Oklobdzija, “Exploration of Switching Activity Behaviour of Addition Algorithms, MWSCAS – 2009, Maxico, August – 2009.

K. Johansson, O. Gustafsson, L. Wanhammar,” Power Estimation for ripple – carry adders with correlated input data”, in proc. Wksp on power timing modelling, optimization, simulation”, Santorini, Greece,sept- 2004.

N.Rollins and M.J.Wirthlin,”Reducing Energy in FPGA multipliers through glitch reduction”, Int. Conference on Military Applications of Programmable Logic Devices, Washington,DC, USA – Sept’ 2005

F. Najm, “A survey of Power Estimation Techniques in VLSI Circuits”, IEEE Trans. VLSI Syst. Vol.2 No.4, pp 446- 455, Dec’1994.

M.Klein,” The Virtex – 4 Power Play,” Xcell Journal, Spring – 2005.

A.P.Chandrakasan, S.Sheng and R.W.Brodersen, “Minimizing Power Computation in Digital CMOS Circuits,” Proc. IEEE, Vol.83, No.4,pp498-523, April -1995.

R. Menon,S.Chennupati, N.K.Samala,D.R.Radhakrisnan and B.Izadi, “Minimization Switching Activity in Combinational Logic Design”, in Proc. Int. Conf. On Embedded Systems and Applications, pp.47-53,2004.

Fei Li, Deing Chen, Lei He, Jason Cong,”Architecture Evolution for Power Efficient FPGAs”, proc. Int.Symp.on FPGA -2003, pp 175-184.

T.English, K.L.Man and Papovici,”A Switching Activity Analysis and Visualisation Tool for Power Optimization of SoC Buses”,PhD Research in Micro Electronics and Electronics, pp. 264 – 267, 2009.

P.Schneider and S.Krishnamoorthy, “Effects of Correlations on accuracy of Power – Analysis – An Experimental Study” Int.Symp. on Low Power Electronics Design,pp. 113-116, California,USA-1996.

C. Baena, J.Juan-Chico, M.J. Bellido, P.Ruiz de Clavijo, C.J.Jimenez and M.Valencia, “Measurement of Switching Activity of CMOS Digital Circuits at the Gate Level”, Springer, Berlin – 2002.

Jan.M.Rabey and M.Pedram,”Low Power Design Methodologies”, Boston, Kluwer Academic -1996.

T.Osmulski, et.al.,”A Probabilistic Power prediction Tool for Xilinx FPGA”, proc. 5th Int.Wksp. on Embedded /Distributed HPC Systems and Applications”, pp. 776-783, May – 2000.

I.Brzozowski and A.Kos,” Minimization of Power Consumption in Digital Integrated Circuit by Reduction of Switching Activity”, 25th Euromicro Conf., vol.1 , Sept’1999.

J. Anderson and F.Najm,” power Estimation Technique for FPGAs”,IEEE trans. On VLSI sys., vol.12, no.10,pp.1015 – 1027, Oct-2004.

C-Y.Tsui, M.Pedram and A.M.Despain,”Efficient Estimation of Dynamic Power Dissipation under a real Delay Model”, in proc.of the IEEE Int. Conf. on Computer Aided Design, pp. 224-228, Nov-1993.

J.Juan-Chico, M.Bellido,P.R. de Clavijo,C.Baena, C.Jimenez and M.Valencia,”Switching Activity Evaluation of CMOS Digital Circuits Using Logic Timing Simulation”, IEEE Electronics Letters, vol.37,No.9, pp.555-557, April- 2001.

R.Marculescu, D.Marculescu and M.Pedram,” Probabilistic Modelling of Dependencies during Switching Activity Analysis”, IEEE Trans. On Computer – Aided Design of Integrated Circuits and Systems, vol.17,no.2,pp.73-83, Feb-1998


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