Bi-Directional Barrel Shifter Using Reversible Gates
Abstract
Keywords
Full Text:
PDFReferences
Irina Hashmi, Hafiz Md. Hasan Babu “An Efficient Design of a Reversible Barrel Shifter” International Conference on VLSI design 2010.
C.H. Bennett, Logical reversibility of computation, IBM J. Res. Dev. 17 (1973) 525-532.
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, AhsanRaja Chowdhury and Syed Mostahed Ali howdhury, “Reversible Logic Synthesis for Minimization of Fulladder Circuit”, IEEE Conference on Digital System Design 2003, Euro-Micro’03, Belek, Antalya, Turkey,2003, pp. 50-54. 97
Voyiatzis, D. Gizopoulos, and A. Paschalis,“Accumulator-Based Test Generation for Robust Sequential Fault Testing in DSP Cores in Near-OptimalTime” , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 9, pp. 1079–1086, September 2005
Paul Metzgen, “Optimizing a High Performance 32-Bit Processor for Programmable Logic”, Proceedings of International Symposium on System on Chip, 16-18 Nov. 2004.
Thomas Conway, “Galois Field Arithmetic OverGF(pm) For High-Speed/Low-Power Error-Control Applications”, IEEE Transactions on Circuits and Systems, Vol. 51, No. 4, April 2004.
Gorgin, S.; Kaivani, A, “Reversible Barrel Shifters,”Computer System and applications, 2007. AICCSA apos;07. IEEE/ACS International Conference on Volume, Issue , 13-16 May 200 Page(s): 479 – 483.
Ashis Kumer Biswas, Lafifa Jamal and Hafiz Md. Hasan Babu, “An Efficient Design of Parallel Loading Shift Register Using Reversible Flip-Flops,” Advanced Technical Program, VLSI-SOC, 16th IFIP/IEEE international conference on very large scale integration, 13-15 October, 2008.
Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu, “Efficient approaches for designing reversible binary coded decimal adders,” Volume 39, Issue 12 (December 2008), p. 1693-1703, ISSN:0026-2692, Elseviercience Publishers B. V.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.