Power Efficient Arithmetic Circuits for Application Specific Processors
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Chandrakasan, P. A., Sheng, S., and Brodersen, W. R. Low-power cmos degital design.IEEE Journal of Solid-State Circuits, 27(4), April 1992.
Benini, L. and De Micheli, G. Dynamic Power Mangement Design Techniques andCAD Tools. Kluwer Academic Publishers, 1998.
Monteneiro, J. and Devadas, S. Computer-Aided Design Techniques for Low PowerSequential Logic Circuits. Kluwer Academic Publishers, 1997.
Meyr, H. and Noll, T. Designing complex socs for wireless communications: More than pushing mops and clock frequency. ISLPED 2002, available at http://www.iss.rwth-aachen.de/5 aktuell/_les/ISLPED public version.pdf, 2002.
Devadas, S. and Sharad, M. A survey of optimization techniques targeting low powervlsi circuits. 32nd ACM/IEEE Design Automation Conference.
Kang, M. S. Accurate simulation of power dessipation in vlsi circuits. IEEE Journal of Solid-State Electronics, 21(5):889{891, October 1986.
Bellaouar and M. Elmasry, Low-power Digital VLSI Design: Circuitsand Systems. Kluwer Academic Publishers, 1995
G.K. Yeap, Practical Low Power Digital VLSI Design. Kluwer Academic Publishers, 1998.
J. Frenkil, “A multi-level approach to low-power IC design,” IEEE Spectrum Magazine, pp.54-60, Feb. 1998.
T. Lang, E. Musoll, and J. Cortadella, “Individual flip-flops with gated clocks for low power datapaths,” IEEE Trans. Circuits and Systems – II:Analog and Digital Signal Processing, vol.44, no.6, pp.507-516, June 1997.
T. Sakuta, W. Lee, and P.T. Balsara, “Delay balanced multipliers for low power/low voltage DSP core,” in Proc. 1995 IEEE Symp. Low Power Electronics,pp.36-37, Oct. 1995.
M.K. Gowan, L.L. Biro, and D.B. Jackson, “Power considerations in the design of the Alpha 21264 microprocessor,” in Proc. 35th Design and Automation Conf, pp.726-731, 1998.
T. Xanthopoulos and A.P. Chandrakasan, “A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity,” IEEE J. Solid-State Circuits, vol.34, No.5, pp.693-703, 1999.
Wu Ye and M.J. Irwin, “Power analysis of gated pipeline registers,” in 12th Annual IEEE Int. ASIC/SOC Conf, pp.281-285, 1999.
J. Monteiro, S. Devadas, and A. Ghosh, “Retiming sequential circuits for low power,” in Proc. 1993 Int. Conf. Computer-Aided Design, pp.398-402,Nov. 1993.
A.P. Chandrakasan and R.W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” Proceedings of the IEEE, vol.83, no.4, pp.498-523, Apr. 1995.
Landman, P. High-level power estimation. IEEE/ACM Int. Symposium on Low PowerElectronics and Design, pages 29{35, 1996.
Najm, F. and Xakellis, M. Statistical estimation of the switching activity in digitalcircuits. ACM/IEEE Design Automation Conference, pages 728{733, 1994.
Anantha. P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, “Low-Power CMOS digital design(1992),” IEEE Journal of Solid-State Circuits, Vol 27, No. 4, April, 1992
Neil H.E. Weste ,and David Harris, CMOS VLSI Design: a circuits and systems perspective, Addison-Wesley Publishing Company, 3rd ed.
S.J. Jou, C.Y.Chen, E.C. Yang, and C.C.Su(1995), “A pipelined Multiplier-accumulator using a high speed, low power static and dynamic full adder design”, IEEE Custom Integrated circuit conference, 1995, pp. 593-5961
Bill Moyer, “Low Power Design for Embedded Processor”,Proc. of IEEE, Vol.89, No.11, 2001, pp.1576-1586.
VLSI Design and Implementation of Low Power MAC Unit with Block Enabling Technique. European Journal of Scientific Research ISSN 1450-216X Vol.30 No.4 (2009), pp.620-630 © EuroJournals Publishing, Inc. 2009
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