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Optimizing Digital Circuit Leakage Current Using MTCMOS Technique

Shailaja D. Bardale, Shivakanth Khandre, Dr. C. M. Tawade

Abstract


Various high speed ordered multi-threshold voltage CMOS (MTCMOS) circuit techniques are conferred and evaluated during this paper. Ground bouncing noise made throughout the sleep to active mode transitions is a vital challenge in Multi-Threshold CMOS (MTCMOS) circuits. Various MTCMOS Circuits are evaluated using DSCH and Micro wind.


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References


Kursun and E. G. Friedman, Multi-Voltage CMOSCircuit Design, John Wiley & Sons Ltd., 2006, ISBN # 0-470-01023-1.

S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V Power SupplyHigh-SpeedDigitalCircuit Technology,” IEEE Journal ofSolid-State Circuits, Vol. 30, No. 8, pp. 847-854,August 1995.

J. Kao and A. Chandrakasan, “MTCMOS Sequential Circuits,” Proceedings of the European Solid StateCircuits Conference, pp. 317 - 320, September 2001.

S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits,” IEEEJournal of SolidState Circuits, Vol. 32, No. 6. Pp.861-869, June 1997.

Z. Liu and V. Kursun, “New MTCMOS FlipFlops with Simple Control Circuitry and Low LeakageDataRetentionCapability,” Proceedings of the IEEEInternational Conference on Electronics, Circuits, and Systems, pp. 1276-1279, December 2007.

J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor Sizing Issues and Tool for MultiThreshold CMOS Technology,” Proceedings of the IEEE/ACM International Design Automation Conference, pp. 409 - 414, June 1997.

B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, “A Leakage Reduction Methodology for Distributed MTCMOS,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 2, pp. 818 - 826, May 2004.

S. A. Tawfik and V. Kursun, “Low-Power and Compact Sequential Circuits with IndependentGate FinFETs,” IEEE Transactions on Electron Devices, Vol. 55, Number 1, pp. 60-70, January 2008.

R. Kumar and G. Hinton, “A Family of 45nm IA Processors,” Proceedings of the IEEE International Solid-State Circuits Conference, pp. 58-59, February2009.

Z. Liu and V. Kursun, “High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling,” Proceedings of the IEEE International Systems on Chip (SOC) Conference, pp. 115-116, September 2006.


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