Implementation of Low Power Consumed 64-Bit RISC Processor using Clock Gating

Abstract

In today‘s Integrated Circuits (ICs), Built-In-Self Test (BIST) is becoming increasingly important as designs become more and more complicated. BIST is beneficial in many ways: First, it can reduce dependency on external Automatic Test Equipment (ATE). In addition, BIST can provide at speed, in system testing of the Circuit-Under-Test (CUT). This is crucial to the quality component of testing. BIST can overcome pin limitations due to packaging, make efficient use of available extra chip area, and provide more detailed information about the faults present. On a very basic level, BIST needs a stimulus (the Test Pattern Generator - TPG), a circuit to be tested (CUT) and a way to analyze the results (ORA). Additionally, there may be compression schemes for the TPG and the ORA. A 64 bit RISC processor with limited functionality will design with an architecture that supports BIST. The ALU is analyzed and an exhaustive set of test patterns will develop. Here clock gating technique is used for reducing the power consumption of the design . Some of these applications include vending machines, bottling plants, control of robotic movements, and automatic teller machine (ATM). Cadence tool is used for synthesis and Xilinx ISE is used for simulation.