Open Access Open Access  Restricted Access Subscription or Fee Access

FPGA Implementation of Reed-Solomon Error Correcting Code

Pranali P. Kale, Dr.R.S. Kawitkar

Abstract


Reed-Solomon (RS) is an error-correcting code capable of dealing with correcting multiple errors, specifically burst errors. It is form of special non binary subclass of BCH (Bose, Chaudhari and Hocqueng) codes. It can correct up to (n-k)/2 or t symbols. For a typical channel, the addition of RS coding allows the system to operate within approximately 4 dB of the Shannon capacity. The resulting benefit translates into higher data rates, lower bit error rates, greater transmission distance, and greater immunity to interference effects. Programmable-hardware devices are the best choice for Reed-Solomon codec implementation, because these devices contain an abundance of the registers that the hardware-implementation process requires. They also allow implementing a pipelined design. Secondly, parallel realization of the equations is possible and helps to meet speed constraints. Easily mapping of equations is possible on the LUT architecture of FPGAs.

Keywords


Reed-Solomon Error Correcting Code(RS codes),Forward Error Correction (FEC).

Full Text:

PDF

References


Richard E. Balahut, “Theory and Practice of Error Control Codes”, Addison-Wesely Pub, 1983.

Richard E. Balahut, “Algebric Codes for Data Transmission”, Cambridge Publisher, 2003

S. B. Wicker, V. Bhargava, “Reed Solomon Codes and their Applications”, IEEE Press, 1994.

W.J. Ebel, W. H. Tranter, “The Performance of Reed-Solomon Codes on a Bursty-Noise Channel” IEEE Transactions on Communications, Vol. 43, No. 2/3/4, February/March/April 1995

R. H. Morelos-Zaragoza, “The Art of Error Correcting Coding”, John Wiley & Sons Ltd, p. 1,74, Chichester (2006).

A. Betten, “Error-Correcting Linear Codes: Classification by Isometric and Applications”, p. 7, 4, Springer, Berlin (2006).

J. C. Moreira and P. G. Farrell, “Essentials of Error-Control Coding”, John Wiley & Sons Ltd, p. 2, 166, 3, 166 , Chichester (2006).

M. A. Ingale,’ Error Correcting Codes in Optical Communication Systems”, Gothenburg (2003).

S. S. Shah, “Self-correcting ocodes counquer noise”, Part II: Reed-Solomon codecs, Design Feature, Electronic Design News, March 2001.

H. Chang, C. Shung, C. Li, “A Reed-Solomon Product-Code (RS-PC) Decoder Chip for DVD Applications”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 2, February 2001.

S. B. Wicker, “Error control Systems for Digital Communication and Storage”, Prentice Hall, 1995.

R. K. Awalt., “Making the ASIC/FPGA Decision”, Integrated System Design Magazine, July1999.

G. Ahlquist, B. Nelson, and M.Rice, “Synthesis of Small and Fast Finite Field Multipliers for Field Programmable Gate Array”, Proceeding of 5th annual mliltary and Aerospace programmable logic device International Conference, Sept 2002.

Frederic Rivollon, “Achieving Breakthrough Performance in Vertex-4 FPGA guide”, May 2005.

Hanho Lee, “A High Speed, Low capacity Reed Solomon decoder for optical communication”, IEEE Transaction on circuits and System II, 2005.

B. Thomson,“Turbo Product-Coding Hardware Makes Forward-Error Correction Possible with Significant Performance Advantages over Traditional Reed-Solomon and Viterbi Coding Approaches” ,Wireless Systems Design, June 2000

T. A. Mehta, “Programmable Logic Devices : Viable Solutions for Implementing Error-Control Coding Functions”, Integrated System Design Magazine.

E. J. Weldon, “Error Correcting Codes and Trellis coded Modulation”, University of Hawaii, 1996.

K. C. C. Wai and S. J. Yang, “Field Programmable Gate Array Implementation of Reed-Solomon Code, RS(255,239)”, New York(2006).

A. Ferreira, “Aplicação da Teoria dos Campos de Galois na Codificação de Canal”, Lisboa (1999).


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.