Low Power Low Area Novel Multiplier for DSP Applications

Abstract

The Multiply-accumulate (MAC) unit is one of the basic components in any DSP applications like filtering, FFTs and DCT cores. The design units of MAC consist of Multiplier and Accumulator unit. The multiplier plays major role in the design of MAC unit and the fundamental constraints that are imposed in the design of multiplier unit are area and power consumption. These constraints determine the logic families used to make the Multiplier, as well as the algorithm used for the multiplier circuits. One such multiplier circuit is the Booth Multiplier, which reduces the number of cycles per operation and area, but which consumes more power. In our project, we will design a novel Multiplier which meets the requirements of low area and low power. One of the most important design choices to make will be the logic family in case of ASIC. We propose another modification to increase the speed: incorporating the pipeline structure. This module can be developed in FPGAs. We will use the Verilog tool to design the module in FPGA. The simulators used for this will be Xilinx ISE13.1.