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Modeling and Analyzing Cache for Multi-Core Processor

Ram Prasad Mohanty, Ashok Kumar Turuk, Bibhudatta Sahoo

Abstract


The growing number of cores increases the demand for a powerful memory subsystem. This lead to enhancement in the size of caches in multi-core processors. Caches are responsible in giving processing elements a faster, higher bandwidth local memory to work with. In this paper, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on NIAGRA architecture. The SPLASH-2 benchmark has been used with the simulator Multi2Sim for these experimentations.

Keywords


Cache Configuration, Performance Evaluation, Multi-Core Processor, Performance Enhancement.

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