MORA - Based Processor with Low Power Consumption and Small Area Requirement

Abstract

The MORA architecture can be used to implement an 8-bit processor core to be a part of the power efficient multimedia oriented reconfigurable architecture reconfigurable array. The multimedia applications which means video and audio application. The processor shows a peak throughput performance of 75mops/mw. The processor having mainly processing element unit, control unit, and memory. The power consumption of the processor can be reduced by using the segmented memory (separated read memory and write memory) instead of the dual port memory.  Which means that by using the read write enable signal the processor can choose read operation or write operation on the interest of the user. When the read memory is in the ‘on’ condition the write memory will be in the ‘off’ condition and vice versa. By using this technique we can reduce the power consumption about 40% than other existing processors. The area of the processor is a big feature during the selection of the processor. The area of the processor can be decreased by changing the Wallace tree multiplier in the processing element unit. By using the half adder and full adder instead of the ripple carry adder then the area will be reduced. About 15% of the area can be reduced by implementing this method. The area of the processor is estimated by the number of logics used and number of flip flops used etc. Our analysis shows that this processor is more efficient than the other processors.