Testing the Pattern Generation of Minimal Test Vectors for the Video Display
Abstract
Keywords
Full Text:
PDFReferences
K. Smita, F. V. George, L. M. Igor, and P. H. John, "Probabilistic transfer matrices in symbolic reliability analysis of logic circuits," ACM Trans. Des. Autom. Electron. Syst., vol. 13, pp. 1-35, 2008.
W. Laung-Terng, W. Cheng-Wen, and W. Xiaoqing, VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon): Morgan Kaufmann Publishers Inc., 2006.
D. H. Gary and S. Fabio, Logic Synthesis and Verification Algorithms: Springer-Verlag New York, Inc., 2006.
V. Shireesh, R. Kiran, and G. H. Ian, "An efficient control-oriented coverage metric," in Proceedings of the 2005 conference on Asia South Pacific design automation Shanghai, China: ACM, 2005.
K. J. Sunil and D. A. Vishwani, "Test generation for MOS circuits using D-algorithm," in Proceedings of the 20th conference on Design automation Miami Beach, Florida, United States: IEEE Press, 1983.
C. P. Ravikumar, M. Hirech, and X. Wen, "Test strategies for low power devices," in Proceedings of the conference on Design, automation and test in Europe Munich, Germany: ACM, 2008.
E. Sanchez, M. Schillaci, M. S. Reorda, G. Squillero, L. Sterpone, and M. Violante, "New evolutionary techniques for test-program generation for complex microprocessor cores," in Proceedings of the 2005 conference on Genetic and evolutionary computation Washington DC, USA: ACM, 2005.
O. Goloubeva, M. S. Reorda, and M. Violante, "Automatic Generation of Validation Stimuli for Application-Specific Processors," in Proceedings of the conference on Design, automation and test in Europe - Volume 1: IEEE Computer Society, 2004.
P. Bernhard and W. Franz, "Error traces in model-based debugging of hardware description languages," in Proceedings of the sixth international symposium on Automated analysis-driven debugging Monterey, California, USA: ACM, 2005.
P. Irith and M. R. Sudhakar, "Test vector chains for increased targeted and untargeted fault coverage," in Proceedings of the 2008 conference on Asia and South Pacific design automation Seoul, Korea: IEEE Computer Society Press, 2008.
S. Saeed, E. Hadi, and N. Zainalabdein, "Instruction-level test methodology for CPU core self-testing," ACM Trans. Des. Autom. Electron. Syst., vol. 10, pp. 673-689, 2005.
“RTL-to-Gates Synthesis Using Synopsys Design Compiler (March 2008),”[Online].Available:http://csg.csail.mit.edu/6.375/handouts/tutorials/tut4-dc.pdf.
B. Rahbaran, A. Steininger, and T. Handl, “Built-in Fault Injection Hardware – The FIDYCO Example,” Proc. of the IEEE International Workshop on Electronic Design, Test and applications, Jan. 2004, pp. 327-332.
“Opencores”, http://www.opencores.org, [accessed: July 2007].
T. A. Delong, B. W. Johnson, and J. A. Profeta, Iii, “A fault injection technique for VHDL behavioral-level models,” Proc. of the IEEE Design & Test of Computers, 1996, pp. 24-33.
“Stratix EP1S25 DSP Development Board”, available at: http://www.altera.com/literature/ds/ds_stratix_dspboard- starter.pdf”, [accessed: Sep. 2007].
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.