P-Match: A Microprocessor Cache Compression Algorithm

Abstract

Speed of microprocessors is being increasing faster than speed of off-chip memory. When multiprocessors are used in the system design, more processors require more accesses to memory. Thus acts as a barrier between processor and memory. Accessing off-chip memory takes more time than accessing an on-chip cache and much more time than executing an instruction. Cache compression presents the challenge that the processor speed has to be improved but it should not significantly increase the total chip power consumption. This architecture has number of novel features tailored for the application. In the proposed work if there are consecutive zeros or ones then there patterns are encoded and the dictionary matching is bypassed. By this method the speed and the power can be improved without affecting the performance of system cache and the compressed pattern is retrieved at the decompressor output without any loss in data.