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A 3-1 ALU Design to Collapse Interlocks in Parallel Processing for High Performance

Vandana Katta, R. Koteswara Rao Naik, G.V.K. Sharma, M. Murali Krishna


An important area in computer architecture is parallel processing. A parallel machine executes multiple instructions in one cycle. However, parallel machines have a limitation, they cannot execute interlocked instructions. They are executed in serial, and take more than one cycle to execute multiple instructions causing performance degradation. In addition there is hardware underutilization as a result of serial execution in parallel machine. The solution requires a special kind of device to collapse the interlocks; unlike conventional 2-1 ALU‟s is a 3-1 ALU. The proposed device executes the interlocked instructions in a single instruction cycle, unlike other parallel machines, resulting in high performance.. In this paper 3-1 ALU is designed to collapse interlocks using Verilog HDL and the simulation, synthesis results and RTL schematic are viewed in XILINX ISE 8.1 i. ASIC implementation is also verified using Cadence Tools.


Interlocks, Data Hazards, Parallel Processing, Synthesis, Encounter Result, Virtuoso Result.

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