Open Access Open Access  Restricted Access Subscription or Fee Access

Multichannel MAC Unit for DSP Applications

M. Janani Preeyaa, T. V. Karthika, R. Pooja Sree

Abstract


In most of the DSP (Digital Signal Processing) and multimedia communication applications the important operations are multiplication and accumulation. Real time signal processing requires a low power consumption, lower delay and highspeed MAC (Multiplier-Accumulator) unit. Multiply and Accumulator (MAC) unit is the backbone of DSP processors. So its design and performance will define the efficiency of the overall system working and its accuracy. The proposed system is to design Multichannel MAC unit which will achieve high speed multiplication and accumulation by CSA (Carry Save Adder) and Multiplication using Modified Radix 4 Booth Algorithm. Here 4 MAC unit of each 32 bit is integrated parallelly and the input data is given from control logic. Carry Save adder is used to reduce the delay time and Modified Radix 4 Booth multiplication algorithm is used to reduce the partial products with this overall helps in increasing the speed of the MAC. The proposed design is developed, simulated and synthesized using Xilinx ISE showing the results in terms of reduced delay, less power and lower delay


Keywords


Carry Save Adder, Radix-4 Booth Algorithm,4- Channel MAC, Control Logic

Full Text:

PDF

References


T. T. Hoang, M. Sjalander, and P. Larsson-Edefors, “A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and its Application to a Double-Throughput MAC Unit,” IEEE Trans. on Circuits and Systems, vol. 57, no. 12, pp. 30733081, Dec 2010.

C. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. On Electronics and Computers, vol. EC-13, no. 1, pp. 1417, Feb. 1964.

M. S. Schmookler and A. Weinberger, “High Speed Decimal Addition,” IEEE Trans. on Computers, vol. C-20, no. 8, pp. 862866, Aug. 1971.

R. P. Brent and H. Kung, “A Regular Layout for Parallel Adders,” IEEE Trans. on Computers, vol. C-31, no. 3, pp. 260264, Mar. 1982.

W. Chu, A. Unwala, P. Wu, and E. Swartzlander, “Implementation of a High Speed Multiplier using Carry Lookahead Adders,” in Proc. IEEE Asilomar Conf. on Signals, Systems and Computers, Nov. 2013, pp. 400404.

A. V. Oppenheim, R. W. Schafer, and J. R. Buck, “Discrete-time Signal Processing (2Nd Ed.),” Upper Saddle River, NJ, USA: Prentice-Hall, Inc., 1999.

S Deepak; Binsu J Kailath “Optimized MAC unit design “, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC)

S Deepak; Binsu J Kailath “Optimized MAC unit design “, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC)

Priyanka A. Patil; Charudatta Kulkarni; “Multiply Accumulate Unit Using Radix-4 Booth Encoding”; 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS).

S. Ahish; Y.B.N. Kumar; Dheeraj Sharma; M.H. Vasantha,” Design of high performance Multiply-Accumulate Computation unit “ 2015 IEEE International Advance Computing Conference (IACC).

K. Lilly; S. Nagaraj; B Manvitha; K Lekhva; “Analysis of 32-Bit Multiply and Accumulate Unit (MAC) using Vedic Multiplier”; 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)

P. Jagadeesh; S. Ravi; Kittur Harish Mallikarjun,” Design of high performance 64 bit MAC unit ” , 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT)

A. Farooqui and V. Oklobdzija, “General Data-Path Organization of a MAC Unit for VLSI Implementation of DSP Processors,” in Proc. IEEE Intl. Symposium on Circuits and Systems, May 1998, pp. 260263.

O. Chen, N. Y. Shen, and C. C. Shen, “A Low-Power Multiplication Accumulation Calculation Unit for Multimedia Applications,” in Proc.IEEE Intl. Conference on Acoustics, Speech, and Signal Processing,Apr. 2003, pp. II6458.

L. H. Chen, L. H. Chen, T. Y. Wang, and Y. C. Ma, “A Multiplication Accumulation Computation Unit with Optimized Compressors and Minimized Switching Activities,” in Proc. IEEE Intl. Symposium on Circuits and Systems, May 2005, pp. 61186121.

A. Abdelgawad, “Low Power Multiply Accumulate Unit (MAC) for Future Wireless Sensor Networks,” in Proc. IEEE Sensors App. Sym posium, Feb. 2013, pp. 129132

A. Abdelgawad and M. Bayoumi, “High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Processing Applications,” in Proc. IEEE Intl. Symposium on Circuits and Systems, May 2007, pp. 3199 3202.

Negar Akbarzadeh; Somayeh Timarchi; Amir Abbas Hamidi,"Efficient multiply-add unit specified for DSPs utilizing low-power pipeline modulo 2n+1 multiplier",2015 9th Iranian Conference on Machine Vision and Image Processing (MVIP)

H R Spoorthi; C P Narendra; U Chandra Mohan,"Low Power Datapath Architecture for Multiply - Accumulate (MAC) Unit",2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT).

James Garland; David Gregg,"Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks",IEEE Computer Architecture Letters ( Volume: 16, Issue: 2, July-Dec. 1 2017).

Yuke Zhang; Dina El-Damak,"A Reconfigurable Passive Switched-Capacitor Multiply-and-Accumulate Unit for Approximate Computing", 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

P.L. Lahari; M. Bharathi; Yasha Jyothi M Shirur,"High Speed Floating Point Multiply Accumulate Unit using Offset Binary Coding", 2020 7th International Conference on Smart Structures and Systems (ICSSS).

Maroju Sai Kumar; D. Ashok Kumar; P. Samundiswary,"Design and performance analysis of Multiply-Accumulate (MAC) unit",2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014].


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.