Fault Tolerant Secured System Using Efficient ML Decoder/Detector
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R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 3,pp. 301–316, Sep. 2005.
M. A. Bajura, Y. Boulghassoul, R. Naseer, S. DasGupta, A. F.Witulski,J. Sondeen, S. D. Stansberry, J. Draper, L. W. Massengill, and J. N., “Models and algorithmic limits for an ECC-based approachto hardening sub-100-nm SRAMs,” IEEE Trans. Nucl. Sci., vol.54, no. 4, pp. 935–945, Aug. 2007.
G. Boopathi raja Raja,Dr.M.Madheswaran, ”Design of improved majority logic fault dectector /corrector based on efficent LDPC codes”,International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 7, July 2013
S. Ghosh and P. D. Lincoln, “Dynamic low- density parity check codesfor fault-tolerant nano-scale memory,” presented at the Foundations Nanosci. (FNANO), Snowbird, Utah, 2007.
[5] B. Vasic and S. K. Chilappagari, “An information theoretical framework for analysis and design of nanoscale fault-tolerant memories based on low-density parity-check codes,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 11, pp. 2438–2446, Nov. 2007.
H. Naeimi and A. DeHon, “Fault secure encoder and decoder for memory applications,” in Proc. IEEE Int. Symp. Defect Fault Toler. VLSI Syst., 2007, pp. 409–417.
H. Naeimi and A. DeHon, “Fault secure encoder and decoder for nanomemory applications,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 17, no. 4, pp. 473–486, Apr. 2009.
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