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An Improved High Speed ASIC Hardware Design for Lifting Schemes Using Xilinx Platform Studio

B. SriLakshmi, M.V.S.R. Kishore, B. HariKrishna

Abstract


In this paper we propose a technique for software-implementation of an lifting with the goal of getting a customizable lifting DWT-core which can be used as a module in implementing a bigger system irrespective of ones choice of implementation platform. Here we have written the core processor Microblaze is designed in VHDL (VHSIC hardware description language), implemented using XILINX ISE 8.1 Design suite the algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. The test results are seen to be satisfactory. The area taken and the speed of the algorithm are also evaluated. It improves throughput 1.35 times greater than the previous design. The Previous design gives throughput upto 93.47MHz.This Proposed System gives the high throughput and it increases the computation speed. For this application it can be used in image processing applications.

Keywords


UART; VHDL; Softcore; System C Microblaze; Lifting

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References


Xilinx, http://www.xilinx.comlproducts/design.

Xilinx Inc., PicoBlaze 8-bit Embedded Microcontroller UserGuide.http://www.xilinx.comlsupport/documentation/userJluides/ugl29.

Digilent Inc., Digilent Nexys2 Board Reference Manual

Xilinx. Inc., Platform Specification Format Reference Manual, Embedded Development Kit EDK 9.2i

Xilinx Inc. MicroBlaze Reference Manual, version 10.1.

Xilinx Inc. Xilinx ISE and Xilinx EDK tools.

Spartan-3 Starter Kit Board User Guide, Xilinx, Inc.

Embedded System Tools Reference Manual, Xilinx, Inc

Spartan-3 FPGA Family: Complete Data Sheet

Platform Studio User Guide, Xilinx, Inc.

Xilinx. Inc., Platform Specification Format Reference Manual, Embedded Development Kit EDK 9.2i

Xilinx, Embedded System Example, XAPP433, version 2.2, 2006.

M. Vetterli and J. Kovacevic, Wavelets and Subband Coding. Englewood Cliffs, NJ: Prentice-Hall, 1995.

T. Wiegand, G. J. Sullivan, G. Bjentegaard, and A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp. 560–576, Jul. 2003.

G. Karlsson and M. Vetterli, “Three dimensional subband coding of video,” in Proc. ICASSP, New York, 1988, vol. 2, pp. 1100–1103.

C. Podilchuk, N. Jayant, and N. Farvardin, “Three-dimensional subband coding of video,” IEEE Trans. Image Process., vol. 4, no. 2, pp.125–139, Feb. 1995.

Y. Chen and W. Pearlman, “Three-dimensional subband coding of video using the zero-tree method,” in Proc. SPIE VCIP, 1996, vol. 2727, pp. 1302–1309.

D. Taubman and A. Zakhor, “Multirate 3-D subband coding of video,” IEEE Trans. Image Process., vol. 3, no. 5, pp. 572–588, May 1994.

A. Wang, Z. Xiong, P. A. Chou, and S. Mehrotra, “Three-dimensional wavelet coding of video with global motion compensation,” in Proc. DCC, 1999, pp. 404–413.

J.-R. Ohm, “Three dimensional subband coding with motion compensation,” IEEE Trans. Image Process., vol. 3, no. 5, pp. 559–571, Sep. 1994.

J. Tham, S. Ranganath, and A. Kassim, “Highly scalable wavelet-based video codec for very low bit rate environment,” IEEE J. Sel. Areas Commun., vol. 16, no. 1, pp. 12–27, Jan. 1998.

S.-J. Choi and J.Woods, “Motion-compensated 3-d subband coding of video,” IEEE Trans. Image Process., vol. 8, no. 2, pp. 155–167, Feb. 1999.

B. Kim, Z. Xiong, and W. Pearlman, “Low bit rate scalable video coding with 3-D set partitioning in hierarchical tree (3-D SPIHT),”IEEE Trans. Circuits Syst. Video Technol., vol. 10, no. 8, pp.1374–1387, Dec. 2000.

Anirban Das, Anindya Hazra, and Swapna Banerjee, “An Efficient Architecture for 3-D Discrete Wavelet Transform”, IEEE Transactions on circuits and systems for video technology, Vol. 20, No. 2, February 2010.

Chin-Fa Hsieh , Tsung-Han Tsai , Neng-Jye Hsu , and Chih-Hung Lai, “ A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes” Department. of Electronics Engineering, China Institute of Technology, Taipei, Taiwan and Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, IEEE Trans 2004.

Jen-Shiun Chiang, and Chih-Hsien Hsia, “An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme,” IEEE International Conference on Systems and Signals, pp. 528- 531, April 2005, Taipei, Taiwan.


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