Comparative Analysis of Pipelined SHA-1 Algorithm based on Different Methodologies
This paper exhibits pipelined Secure Hash Algorithm (SHA-1) architecture based on different methodologies. Three pipelined architecture based on Iterative, Loop unfolding and Pre-Computation technique are implemented. It also focuses on the minimization on critical path delay by employing fastest adder. The performance of proposed architectures are compared and analyzed in terms of number of slices, operating frequency and throughput. The design and implementation work is performed using VHDL in Xilinx ISE Design Suite 13.2 tool. The proposed implementations are also compared with some previous works and offer better results.
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