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Issue
: April 2009
DOI: PDCS042009001
Title: Binary Particle Swarm Optimization
Algorithm for Functional Partitioning of Embedded
Systems
Authors: M. Jagadeeswari, M.C. Bhuvaneswari
Keywords: Embedded Systems, Particle Swarm
Optimization, Genetic Algorithms, Hardware Software
Partitioning
Abstract:
Hardware software partitioning deals with the
decision to partition a system description to be more
suited to be implemented in special purpose hardware
or software running on a standard processor. This
is the key task of hardware software co-design, as
the decision made at the early stage of the design
process impact directly on the performance and cost
of the system. This paper presents a novel application
of Binary Particle Swarm optimization (BPSO) algorithm
for hardware software partitioning. The algorithm
operates on functional blocks for designs represented
as Directed Acyclic Graph (DAG) with the objective
to obtain a Hardware or Software implementation that
meets performance requirements with a reduced design
cost. Test problems are constructed randomly and the
optimal solutions obtained from BPSO algorithm are
compared with the optimal solutions obtained from
traditional genetic algorithm. Experimental results
show that BPSO is capable of finding optimal solutions
very fast.
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Issue
: April 2009
DOI: PDCS042009002
Title: Design Optimization Methodology
for CMOS Operational Amplifier Using NSGAII
Authors: Ms. M. Shanthi, Dr. M.C. Bhuvaneshwari
Keywords: Analog Circuit Synthesis, Transistor
Sizing, Design Automation, PSPICE, Multi Objective
Genetic Algorithm, Miller OTA
Abstract:
This paper focuses on the synthesis and design
of CMOS operational amplifiers (op amps) using novel
multi objective algorithm. The synthesis of CMOS op-amps
can be translated into a multiple-objective optimization
task, in which a large number of specifications have
to be taken into account, i.e., area, power consumption,
slew rate and gain-bandwidth. A multi-objective algorithm
called elitist non-dominated sorting genetic algorithm
(NSGA-II) is applied to search for multiple optimal
solutions, which includes transistor sizes, bias currents
and compensating capacitance values. The knowledge
of this helps the designer to compare and choose a
compromised optimal solution for automating the operational
amplifier design. The proposed methodology has the
ability to generate in short times constraint satisfying
solutions The algorithm is implemented in C programming
language and PSICE is used to evaluate the required
circuit parameters The simulation results confirms
the efficiency of the NSGA-II algorithm in determining
the device sizes.
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