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Modified Logic Parallel Pipelined Architecture for Enhanced Throughput of Advanced Encryption
Abstract
There is an increasing demand for computer networks from individuals and organization for professional activities. Current secure applications often need encrypted channels with high throughput, of the order of gigabits per second. This paper presents a efficient hardware design increasing throughput for the Advance Encryption Standard (AES) algorithm, using a high-speed pipelined architecture. In this hardware architecture, initially generated keys are stored immediately in a memory block and encryption process implemented in parallel. It reduces the required hardware resources and achieves high-speed performance. In low covered area resources this design performs better. Compared to other pipeline based implementations, its throughput can reach 20.832 Gbit/sec, which is the highest in non-ASIC, non inner round class of pipeline hardware architecture.
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