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Design and Implementation of Low Power and High Performance AES Algorithm using FPGA

R. Meera, K. Kalaiselvi

Abstract


Information security has become an important issues in nowadays. Cryptography plays an important role in the security of data transmission. AES has the advantage of implementation in both hardware and software. The 128 bit AES algorithm can be implemented on FPGA in order to speed up the data processing and reduce time for key generation and achieve performance by maintaining speed and reliability with low area and power.


Keywords


Advanced Encryption Standard (AES), Key Expansion, FSM, FPGA.

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References


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