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A Fault Tolerant On Chip Network

R. Angayarkanni, R. Arunprasath

Abstract


An on-chip network used to support traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. This paper also proposes a fault-tolerant solution for a buffer less network-on-chip, including an on-line fault-diagnosis mechanism to detect faults by using fault tolerant deflection routing algorithm. By removing the excessive overhead of queuing buffers, a compact implementation is achieved and stacking multiple networks to support concurrent permutations in runtime is feasible.

Keywords


Multiprocessors System on Chip, Multistage Interconnection Network, Permutation Networks.

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