Open Access Open Access  Restricted Access Subscription or Fee Access

A Novel VLSI Architecture for FIR Filter Using Urdhwa Multiplier Compressor

Deepak Kumar Patel, Dr. Minal Saxena

Abstract


-High performance digital adder with less power consumption and reduced area is a fundamental design issues for advanced processors. Speed and area are now a days one of the important design issues in digital circuits. One of the fastest adder is Carry Select Adder (CSA) which is used in many processors to perform fast arithmetic function. To increase the efficiency of the adder many different adder architecture designs have been developed. As we know per second millions of operations are performed in microprocessors. So while designing of multipliers, speed of operation is one of most important criteria to be considered. Due to which faster multiplier and high speed architecture of adder plays an vital role in many applications. We, in this paper, proposed a technique for designing of FIR filter using urdhwa multiplier compressor and modified carry select adder. Verification of CSA structure is performed and implemented for 16, 32 and 64 bit filter circuits. Comparing with previous existing structure of adder and our proposed design improves the efficiency of adder. These designs are implemented on Xilinx software.  

Keywords


Ripple Carry Adder (RCA), Carry Select Adder (CSA), Binary to Excess-1 converter (BEC), Compressor, FIR Filter.

Full Text:

PDF

References


Ramkumar and Harish M Kittur, “Low-Power and Area-Efficient Carry Select Adder”, IEEE Transsactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2 Feb 2012.

Ms. S.Manju, Mr. V. Sornagopal “An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic”, 978-1-4673-5301-4/13/$31.00 ©2013 IEEE.

Sajesh Kumar U., Mohamed Salih K. K. Sajith K.,“Design and Implementation of Carry Select Adder without Using Multiplexers”, 2012 1st International Conference on Emerging Technology Trends in Electronics, Communication and Networking 978-1-4673-1627-9/12/$31.00 ©2012 IEEE.

Mr. C.S.Manikandababu “An Efficient CSA Architecture for VLSI Hardware Implementation” IJMIE Volume 2, Issue 5 ISSN: 2249-0558I.

Reza Hashemian “A New Design for High Speed and High-Density Carry Select Adders”IEEE August 2000

R. Uma, M. Mohanapriya, Sharon Paul “Area, Delay and Power comparison of adder topology” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012.

Samiappa Sakthikumaran, S. Salivahanan, V. S. Kanchana Bhaaskaran, V. Kavinilavu, B. Brindha and C. Vinoth, “A Very Fast and Low Power Carry Select Adder Circuit”, 978-1-4244 -8679-3 /11/$26.00 ©2011 IEEE.

Sushma R. Huddar and Sudhir Rao Rupanagudi Kalpana M. “Novel High Speed Vedic Mathematics Multiplier using Compressors” 978-1-4673-5090-7/13/$31.00 ©2013 IEEE

Laxman Shanigarapu, Bhavna P. Shrivastava “Low Power and High Speed Carry Adder” International Journal of Scientific and Research Publication, Vol.3,Issue 8, 2013

Sarabdeep Singh, Dilip Kumar “Design of Area and Power Efficient Modified Carry Select Adder” International Journal of Computer Applications (0975 – 8887) Volume 33– No.3, November 2011

K.. Swarnalatha S. Mohan Das P. Uday Kumar “ An efficient carry select adder with less delay and reduced area using FPGA quartus II verilog design” International Journal of Science, Engineering and Technology Research (IJSETR) Volume 2, Issue 8, August 2013

Pallavi Saxena, Urvashi Purohit, Priyanka Joshi” Analysis of Low Power, Area- Efficient and High Speed Fast Adder” International Journal of Advanced Research in Computer and Communication Engineering,Vol. 2, Issue 9, September 2013

Diljith Muraly, Sunil Jacob, Mr. K Padmakumar “Floating Point Addition using Low Power CSA” International Journal of VLSI and Embedded Systems(IJVESISSN): 2249 – 6556

Z. Abid, H. El-Razouk and D.A. El-Dib, “Low Power Multipliers Based On New Hybrid Full Adders”, Microelectronics Journal, Volume 39, Issue 12, Pages 1509-1515, 2008.

J.Ravi, K. Rama Rao, N. Tirumala “Design of Efficient FIR Filter MAC unit Using Parallel Prefix Adder”, International Journal of Advanced Research in Computer and communication engineering Vol. 3, Sep. 2014

Anna Johnson, Binu Manohar, Anu Philip Mathew “Modified MAC based FIR Filter Using Carry Select Adders” IJESIT Vol. 3, Issue 3, May 2015

Pramod Kumar Mehar et al. “Distributed Arithmetic for FIR Filter implementation on FPGA” Proceedings of IC-BNMT 2011,IEEE


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.