Design of Low Power and High Stable SRAM Cell in 45nm Technology Using Cadence

Abstract

The reduction of the channel length due to scaling increases the leakage current resulting in a major contribution to the static power dissipation. For stability of the SRAM cell good noise margin is required so noise margin is the most important parameter for memory design. The higher noise margin of the cell confirms the high-speed of SRAM cell. In this work, a novel SRAM cell with eight transistors is being proposed to reduce the static power dissipation. When compared to the conventional 6T SRAM the proposed SRAM shows a significant reduction in static power dissipation while produce higher stability. The technique employed for the proposed RAM cell, the operating voltage is reduced in idle mode. This technique leads a reduction of 97.81% on static power dissipation. Cadence Virtuoso tools are used for simulation with 45-nm CMOS process technology.