Email this article 
Open Access
Subscription or Fee Access
A VHDL Implementation of Ternary Arithmetic and Logic Unit for Multi Valued Processor
Abstract
Multi valued processors are promising choices for future computing technology. Multi Valued Logic [MVL] has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research. The switching algebra has expanded from binary to penta level, progressing through ternary and quaternary levels. The processors designed with multi valued logic will revolutionize the digital world. Arithmetic Logic Unit [ALU] forms an inherent entity of every processor. This paper presents a novel and an efficient technology dependent method for defining, analyzing, testing and implementing vectored ternary ALU using Very-High-Speed Integrated Circuits, VHSIC Hardware Description Language [VHDL]. The implementation of sub-program overloading feature in the proposed Ternary ALU [TALU] makes its design unique, flexible and portable for further extension. The designed 4 – trit TALU performs a variety of arithmetic and logical operations. The timing performance of the proposed TALU signifies encouraging results that will pave the path for further developments in ternary processors.
Keywords
References
Iwai, H.: ‘CMOS Technology – year 2010 and beyond’, IEEE Journal of Solid State Circuits, SC -34, 3, 1999, pp. 357-366.
Rizwan, B.: ‘Current mode signally in deep sub-micrometer global interconnects’, IEEE transactions on very large scale integration (VLSI) systems, 11(3), 2003, pp. 406-417.
Stephen, H.: ‘High speed digital system design’, John Wiley and Sons, Inc. 2000, pp. 74-90.
Sheng, L., Yong-Bin, K., Fabrizio, L.: ‘CNTFET- based design of ternary logic gates and arithmetic circuits’, IEEE transactions on nanotechnology, 10(2), March 2011.
M. A. H. Abdul Karim “A ternary J-K memory”, Proc. IEEE ISMVL pp. 221-225, May 1976.
R. E. Miller “Switching theory, John Wiley, 1965”
Serran, N., Martins, J., Dias, J.: ‘A proposal for the implementation of ternary digital circuits ’ , microelectronics Journal 28, 1197, pp. 533-541.
Satish Kumar, A., Sweta Priya, A., ‘Modeling of combinational circuits based on ternary multiplexers using VHDL’, International journal of computer science and engineering, 2(5), 2010, 1777-1791.
Masahiro, S., Mititada, M., ‘A study of ternary fuzzy processor using neural networks’ ISCAS'97., Proceedings of 1997 IEEE International Symposium on circuits and systems,1, pp. 613-616.
Balla et al, “Low power dissipation MOS Ternary Logic Family”, IEEE Journal of solid State Circuits, vol. 19,no. 5, pp: 739- 749, October 1984.
Milton R., Martins, E., Richardi, S. ‘Multiple valued logic Algebra for the synthesis of digital circuits’ 39th international symposium on multi-valued logic , ISMVL, 2009, May 2009, pp 262-267
Rashmi, D., Pravin, D., Sonali, D.: ‘TFET based ternary logic gates and arithmetic circuits’, National conference on innovative paradigms in engineering and technology, (pub. Int. journal of computer applications )
Raychowdhury, A., Kaushik, R.: ‘A novel multiple valued logic design using ballistic carbon nanotube FETs’ , Proc. of the 34th IEEE int. symposium on multiple valued logic (ISMVL ‘04), pp 14-19.
Mozammel, K.: ‘Quantum ternary parallel adder / subtractor with partially –look-ahead carry’ Journal of system architecture, 2007, pp 453-464.
Mozammel, K.: ‘A recursive method for synthesis quantum / reversible quaternary parallel adder/ subtractor with look-ahead carry’ Journal of system architecture, 54 (2008) pp. 1113-1121.
Nascimento L.: ‘An automated tool for analysis and design of MVL digital circuits’, 14th IEEE Symposium on Integrated Circuits and Systems Design, 2001,pp. 52-57
Dhande, A., Jaiswal, R., Dudam, S.: ‘Ternary Simulator Using VHDL’, 4th International conference sciences of electronic technologies of Information and Telecommunications, March 2007, Tunsia. pp 1-7.
Dhande, A., Ingole, T.: ‘Design and implementation of 2 bit ternary ALU slice’ 3rd International conferences sciences of electronics, technologies of information and telecommunication, march 2005, Tunsia pp. 1- 11.
Rozon, C.: ‘On the use of VHDL as a multi-valued logic simulator’. Multiple-Valued Logic, 1996. Proceedings of 26th International Symposium on. IEEE, 1996, pp 110-115.
Ali, H., Hamdam, M., Rashid, M., Hamied, H., Issa, A., Kassem, A.: ‘A novel neural network ternary arithmetic logic unit’, The 23rd international technical conference on circuits / systems, computers and communications (ITC-CSCC 2008), pp. 593-596.
Gorde, K., Deshmukh. P.: ‘Design and Simulation of Ternary Logic Based Arithmetic Circuits’,Proceedings of the 2009 International Conference on Signals, Systems and Automation (ICSSA 2009). Universal-Publishers. com, 2010.
Kotiyal, S., Himanshu, T., Nagarajan, R.: ‘Design of A ternary barrel shifter using multiple valued reversible logic’, Proceeding of 10th IEEE international conference on nanotechnology joint symposium with nano korea 2010, pp. 1104-1108.
VHDL Programming by example, D. L Perry, Tata McGraw hill, 4th edition
http://docs.oracle.com/cd/B10500_01/appdev.920/a96624/08_subs.htm#563 (Subprogram overloading)
Frederic Mailhot, Ph.D thesis ‘Technology mapping for VLSI circuits exploiting Boolean properties and operations’, Dec 1991.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.