Reduced Reconfiguration Overheads and Area Utilization of Reconfigurable Systems by Configuration Locking

Abstract

A virtual hardware resource is provided by dynamically reconfigurable Field Programmable Gate Array (FPGA) where the hardware circuits can be scheduled dynamically to the available resources. Significant performance and energy overheads are involved in reconfiguring an FPGA. The relationship between several hardware task scheduling algorithms and their impact on the amount of reconfigurations required to execute a set of hardware tasks is shown in this paper. By selectively locking the configurations within the reconfigurable tiles of an FPGA, the number of reconfigurations required can be reduced. Working area of the tiles can be improved and utilized for more number of tasks by assigning specific range of tiles for every task set.