Open Access Open Access  Restricted Access Subscription or Fee Access

Review Paper on Techniques for Reducing Jitter in PLL

Utsav H. Bhatt, Ekata Mehul, Anurag P. Lakhlani, Amit  Kumar

Abstract


The paper present various possible jitter reduction technique while designing a Phase Locked Loop. Basic block which makes Phase Locked Loop are Phase detector, Loop Filter and Voltage Control Oscillator including suitable feedback. While reducing the jitter of PLL at the output, reduction in bandwidth of loop filter reducing the gain of phase detector, reducing the gain of the VCO, modifying basic building block and several other technique is proposed.


Keywords


Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge-Pump (CP), Current Starved Voltage Control Oscillator (CSVCO).

Full Text:

PDF

References


Silicon Laboratories, “Calculating Total output jitter,” pp. 1–6, 2012.

J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” Solid-State Circuits, IEEE J., vol. 31, no. 11, pp. 1723–1732, Nov. 1996.

A. Telba and S. M. Qasim, “Experimental Results for Low-Jitter Wide-Band Dual Cascaded Phase Locked Loop System,” vol. II, pp. 16–20, 2010.

Analog Devices, “Fundamentals of Phase Locked Loops (PLLs),” pp. 1–10, 2009.

K. H. Madhusudan Kulkarni, “Design of a Linear and Wide Range Current Starved Voltage Controlled Oscillator,” vol. 2, no. 1, pp. 23–30, 2013.

M. Hsieh and G. Sobelman, “Comparison of LC and Ring VCOs for PLLs in a 90 nm Digital CMOS Process,” Proceedings, Int. SoC, 2006.

S. D. Vamvakos, C.Werner, and B. Nikolic. Phase-Locked Loop Architecture for Adaptive Jitter Optimization. In Proc. of the Int’l. Symp. on Circuits and Systems, volume 4, pages 161 – 164, May 2004.

B. Y. Hari and V. Venkatanarayanan, “JITTER REDUCTION CIRCUITS TO REDUCE THE BIT-ERROR RATE OF (SERDES) CIRCUITS Written under the direction of Jitter Reduction Circuits to Reduce the Bit-Error Rate of High-Speed Serializer-Deserializer (SERDES) Circuits,” 2008.

R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, Third Edition. 2010.

B. Razavi, DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS. McGraw Hill Education (India) Private Limited (12 October 2002).

T. Pialis and K. Phang, “Analysis of timing jitter in ring oscillators due to power supply noise,” Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ’03, vol. 1. 2003.

P. Heydari, “Analysis of the PLL jitter due to power/ground and substrate noise,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 51, no. 12, pp. 2404–2416, 2004.

K. M. Ware, H.-S. Lee, and C. G. Sodini, “A 200-MHz CMOS phase-locked loop with dual phase detectors,” IEEE J. Solid-State Circuits, vol. 24, No.6, pp. 1560-1568, 1989.

M. M. M. Curtin and P. O. Brien, “Phase-Locked Loops for High-Frequency Receivers and Transmitters – Part 2,” Analog Dialogue, vol. 3, no. 33, pp. 1–5, 1999.

S. D. Vamvakos, C. Werner, and B. Nikolic, “Phase-locked loop architecture for adaptive jitter optimization,” 2004 IEEE Int. Symp. Circuits Syst. (IEEE Cat. No.04CH37512), vol. 4, 2004.

B. Razavi, “RF microelectronics,” Microelectronics Journal, vol. 29, no. 12. PEARSON, pp. 932–934, 2012.


Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.