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Comparison of Leakage Current at Deep Sub Micron Technologies in CMOS Digital Circuit

Uday Panwar, Kavita Khare

Abstract


High leakage current in Deep-Sub Micron (DSM) regimes is becoming a significant contributor to power dissipation of CMOS circuit parameters are reduced. This paper focusing on the leakage current which is highly dependent on potential applied on the transistors gate. That’s why it can be said that input of the logic gate is able to control the leakage of the gate appropriately during run time of the device. Consider the input vector methodology to analyse NAND logic with 2 inputs using HSPICE simulator with BPTM technologies (i.e. 180nm, 130nm, 90nm, 65nm, 45nm) model. It gives the similar behaviour of leakage current with every technology models. Hench we can shift the logic gate input with its Minimum Leakage Vector (MLV) during run time of the device. Above technique is process parameter independent and there is no need of any extra power supply to reducing the leakage. 


Keywords


Leakage Current, MLV, Input Vector Control

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References


Abdoul Rjoub , “ A fast input vector control approach for sub-threshold leakage power reduction”, Almotasem Bellah Alajlouni, Hassan Almanasrah, 2012.

J. Halter and F. Najm, “A Gate-Level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits,” Proc. Of ClCC, pp.475-478, 1997.

Behnaz Mortazavi, “Modeling leakage in sub-micron CMOS technologies” Azad University of Tehran-Iran, Jun. 1995.

L. Wei, et.al, “Design and optimization of low voltage high performance dual threshold CMOS circuits,” Proc. Of DAC, pp. 489-494, Jun. 1998.

S. Mutoh, et.al, “I-V Power Supply High-speed Digital Circuit Technology with Multi-Threshold Voltage CMOS”, IJSSC, vol. 30, no. 8, pp. 847-854, Aug. 1995.

] T. Kurado, et.al, “A 0.9V, 150 MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold (Vt) Scheme,” IEEE Journal of Solid Stare Circuits, vol. 3 1, no. 11, pp. 1770 - 1779, Nov. 1996.

F. Assaderaghi,“DTMOS: Its Derivatives and variations, and their Potential Applications,” Proc. of 12th Intnl. Conference on Microelectronics, pp. 9-19, 2000.

D. Duarte, Y. Tsai, N. Vijaykrishnan and M. Irwin, “Evaluating Run-Time Techniques for Leakage Power Reduction,” Proc. Of 15th Intnl. Conjerence on VLSI Design, pp. 31-38,2002

A heuristic to search a low leakage vector for CMOS circuits”, Rahul M.Rao, Frank Liu, Jeffrey L.Burns, Richard Brown, Austin research labs, 2006.

Nikhil Jayakumar, “ An algorithm to minimize leakage through simultaneous input vector control and circuit modification”, Sunil P Khatri, Texas, 2007.

F. Aloul, S. Hassoun, K. Sakallah, D. Blaauw, “Robust SAT-BasedSearch Algorithm for Leakage Power eduction,” PATMOS, 2002.


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