An Efficient Implementation of Low-Power Logic Functions using Novel GDI Cells

Abstract

In this paper a CMOS compatible novel Gate Diffusion input (GDI) logic structure is proposed. A novel GDI cell structure is quite similar to a CMOS inverter which has three input ports and one output port. The novel GDI logic is a low power design technique, which enables the implementation of a wide range of logic functions compared to the originally proposed basic GDI cell. This method allows reducing power consumption, delay and area for the design of basic logic gates and few logic functions by using lesser number of transistors than static CMOS logic, while maintaining low complexity of logic design. Logic gates are the basic building blocks for any type of circuit design. So, it is necessary to implement logic gates with minimum power consumption by reducing the transistor count for which novel GDI is a suitable technique to use. A variety of logic gates and functions have been implemented in 1.25 μm CMOS technology. A comparison between static CMOS logic and the proposed novel GDI cell designs has been analyzed. In comparison with conventional static CMOS logic, the novel GDI logic cells achieve reduction in power consumption as well as reduction in power delay product.