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A Power Efficient Pulse Triggered Flip-Flop by X-OR Based Clock Gating Scheme at 32nm Technology
Abstract
A continuous increase in number of transistors and operating frequency causes high power dissipation. The most important task to minimize the power is optimization of power at the logic level. This paper presents a novel power efficient pulse triggered flip-flop. Proposed flip-flop use Exclusive-or gate based clock gating scheme that reduce the power dissipation by disabling the clock signal in inactive portion of chip. In this paper replica path delay pulse generator is used to simplify the design effort. This paper presents a comparison of existing flip-flop in term of power dissipation for different input patterns. The operation of flip-flop is analyzed and is simulated using Tanner EDA in 32nm technology at room temperature in schematic level. Simulation result shows the sensible power dissipation reduction.
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References
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