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Implementation of ALU Using Low Power Full Adder and Multiplexer
Abstract
Arithmetic logic unit (ALU) is an important part of microprocessor. In digital processor logical and arithmetic operation executes using ALU. In this paper we describes 8-bit ALU using low power 11-transistor full adder (FA) and Gate diffusion input (GDI) based multiplexer. By using FA and multiplexer, we have reduced power and delay of 8-bit ALU as compare to existing design. All design were simulated using Tanner EDA tool v15.0 in 32nm BSIM4 technology. 32nm technology introduced metal gate and high-k dielectric Performance analyses were done with respect to power supply 0.9V.
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References
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