A Novel Energy Recovery and Clock Gating Scheme for a Low Power Clock Network

Abstract

A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low power clocking schemes are promising approaches for low-power design. Four novel energy recovery clocked flip-flops have been proposed that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. Clock gating solutions for energy recovery clocking was also proposed. Applying our clock gating to the energy recovery clocked flipflops reduces their power by more than 1000x in the idle mode with negligible power and delay overhead in the active mode. Finally, a test chip containing two Linear Feedback Shift Register (LFSR) one designed with conventional square wave clocked flip-flops and the other one with the proposed energy recovery clocked flip-flops is fabricated and measured.