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Building n-bit ADC Using ADC General Cell Architecture in Two Different Configurations with Sample Circuit Implementations
Abstract
This work introduces a new general architecture for an Analog to Digital Converter (ADC) cell. Each ADC cell generates one digital output bit when an analog voltage is applied at its input and produces an analog voltage. This analog voltage is suitable to be used as an input for another ADC cell in order to produce another digital output bit. This new ADC cell architecture is used as a building block to construct n-bit ADC in two different architectures. The first architecture uses n ADC cells to realize n-bit ADC and generates parallel digital output. The second architecture uses only one ADC cell to achieve n-bit ADC and creates n-bit serial digital output. A sample circuit realization is presented for each n-bit ADC and supported by simulation results. The first ADC architecture produces clean digital output when simulated at 50 Msample/sec while the other ADC architecture is simulated at 5Ksample/sec.
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