Email this article 
Open Access
Subscription or Fee Access
Comparison of Multiplier Design with Various Full Adders
Abstract
A multiplier has an important role in various arithmetic operations in the applications of digital signal processing which includes digital filtering and power analysis in the field of communication. The design of fast and low power multipliers has been a huge theoretical and practical concern for scientific researchers. In this paper the analysis of 4*4 Array and 4*4 Wallace tree multiplier and comparison is being done by using different full adders namely Conventional full adder, Transmission function full adder and Hybrid full adder. This work has been done in a schematic editor using Tanner tool v14.1 in 0.18nm CMOS technology. T-spice is used as simulator and W-editor is used to show the waveform of multiplier. The material area required to design a multiplier is reduced. Due to the reduction of material area, this causes the low power consumption, minimized area and time delay.
Keywords
References
Ron S., Waters and Earl E.Swartzlander-A Reduced Complexity Wallace multiplier reduction, IEEE transactions on Computers, 2010.
Pallavi Saxena, UrvashiPurohit, Priyanka Joshi -Analysis of Low Power, Area- Efficient and High Speed Fast Adder, International Journal of Advanced Research in Computer and Communication Engineering Vol. 2, Issue 9.
SohanPurohit and Martin Margala -Investigating The Impact Of Logic And Circuit Implementation On Full Adder Performance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 7, 2012 .
Rajaram, S. and Mrs.K.Vanithamani -Improvement of Wallace multipliers using Parallel prefix adders. Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies IEEE, 2011.
C.Saranya, R.Naveen, K.Thanushkkodi -Leakage Power Reduction In Wallace Tree Multiplier Using Current Comparison Based on Domino Logic Full Adders, in Journal of Theoretical & Applied Information Technology Vol.55, No.1, September 2013.
J. Murugabharathi, M. Kalaiyarasi, Anusuyadevi, S. Kaliaivani -Systematic Analysis on Power Consumption in Conventional CMOS, Multiplexer Based Hybrid Adder, IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278- 2834, p-ISSN: 2278-8735. Volume 4, Issue 6 , PP 89-93, 2013.
Belle W.Y. Wei and Clark D. Thompson -Area &Time Optimal Adder Design, IEEE transactions on Computers, volume 39, pp. 666-675, May1990.
Prakash S P, SaroRamya S, Sakthivel S -Design and Comparison of Array and Tree Multiplier Using Different Logic Styles, International Journal of Engineering & Innovative Technology (IJEIT) Volume 2, Issue 7, 2013.
Sandeep Kakde -Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier, IEEE International conference on pervasive computing.
Massimo Alioto and Gaetano Palumbo. “Analysis and Comparison on Full Adder block in Submicron technology”. IEEE transactions on very large scale integration (VLSI) systems, vol. 10, no.6, december 2002.
Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung “A Novel Multiplexer-Based Low-Power Full Adder.” IEEE transactions on circuits and systems, vol. 51, no. 7, july 2004.
Kang, S., ―Accurate simulation of power dissipation in VLSI circuits,‖ IEEE Journal of Solid-State Circuits, vol. 21, 1986, pp. 889-891.
A. Chandrakasan, S. Sheng and R. Brodersen, (1992)“Low-power CMOS digital design,” IEEE Journal of Solid State Circuits, Vol. 27, No 4, pp. 473-484.
K. Navi, O. Kavehie, M. Rouhulamini, A. Sahafi, and S. Mehrabi, “A novel CMOS full adder,” in Proc. 20th Int. Conf. VLSI Design, 2007, pp. 303– 307.
K. Y. Kyaw, W. L. Goh, and K. S. Yeo, “Low-power high-speed multiplier for error-tolerant application,” in IEEE Intl. Conf. Electron Devices and Solid-State Circuits (EDSSC), 2010, pp. 1–4.
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.