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A 6.7mW 8-bit Power Optimzed Sigma-Delta ADC As DUT for Built-in-Self-Test in 45nm CMOS
Abstract
Design and testing of oversampling sigma-delta (ΣΔ) Analog to digitals converter is graeat challenge is in todays mixed signal ICs . In this paper a contemporary design for 8-bit ΣΔoversampling ADC is presented, in which first order oversampling ΣΔ modulator and the decimation filter is second order CIC (Cascaded Integrated Comb) filter which is used. Transistor level circuit design and output simulation of the sigma-delta ADC with a power supply of 1V is presented here. This architecture is implemented by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology is used as DUT (design under test )block of Built -in -self -test realization of ADC.
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References
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