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FPGA Implementation of Decimal Frequency Divider Using I2C

K. L. V. Ramana Kumari, K. Swetha Reddy, Satya Kumar Mitte

Abstract


The divider is one of the most important module in microprocessors. A new algorithm is developed to realize the decimal frequency divider with non-integer dividing factor, and it can be configurable by the Inter-Integrated Circuit (I2C/IIC).  The dividing factor is adjusted dynamically by calculating the error of frequency. Error of frequency can be reduced and high accuracy can be achieved after five rounds of Division. The implementation of decimal frequency divider is realized with Artix-7 FPGA. The experimental result indicated that the decimal frequency divider gives low error of frequency that can be ignored. So high accurate decimal frequency divider can be designed and implemented on FPGA using I2C.


Keywords


Decimal Frequency Divider, I2C, FPGA, Error of Frequency.

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References


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