Email this article 
Open Access
Subscription or Fee Access
Comparative Analysis of Different Full Adder Circuits
Abstract
Multiplier is the most commonly used circuits in the microprocessor and digital signal processors. The demands for low-power VLSI systems are increasing rapidly. . The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. Now a days, there are an increasing number of portable applications requiring small area, low power and high throughput circuitry. With the explosive growth in laptops, portable personal communication systems (PCS‟s) and evolution of the shrinking technology & flexible circuits, the circuits with low power consumption become the major problem for the design of microprocessor and system components. The adders and multipliers are the basic elements to construct the ASIC applications. In this regard a full adder circuits is the most important one, since it forms the basic element in any digital designs. Full adder is the main block of power dissipation of multipliers. In this paper five different full adder circuits are compared using EDA Tanner(Evaluation Version), simulations are base on 180nm CMOS technology.
Keywords
References
N.Weste and K.Eshraghian, Principles of CMOS digital design. Reading, MA: Addison-Wesley, pp. 304–307.
A. P. Chandrakasan, S.Sheng, and R. W Brodersen, “Low- power CMOS Design,” IEEE J. Solid-State Circuits, vol. 27, pp. 473–484,Apr.1992.
A.P.Chandrakasan and R.W. Bordered, “Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, vol. 83, No. 4, pp. 498– 523, Apr. 1995.
A.Morgenshtein, A. Fish, I. A. Wanger,” Gate- Diffusion Input (GDI):A power efficient method for digital combinational circuits”, IEEE Tran. On Very Large Scale Integration (VLSI), Vol. 10, No. 5, 2002, pp. 566-581.
W.C.Athas and N.Tzartzanis, “Energy Recovery for Low-Power CMOS”, Proc.Of 16thConference on Advanced Research in VLSI, 1995, pp. 415- 429,
Ricardo Gonzalez, Benjamin M. Gordon, and Mark A. Horowitz, “Supply and Threshold Voltage Scaling for Low Power CMOS”, IEEE J. Solid-State Circuits, Vol. 32, No. 8, Aug. 1997, pp. 1210-1216.
Q. Wu, P. Massoud, X. Yu, “Clock-Gating and Its Application to Low Power Design of Sequential Circuits,” Proc. of the IEEE Custom Integrated Circuits Conference, 1997, pp. 425- 435.
V. Gutnik, A. Chandrakasan, “Embedded Power Supply for Low-Power DSP,” IEEE Transactions on VLSI Systems, Vol. 12, pp.425-435, Dec. 1997
Wang,A.P.Chandrakasan,S.V.Kosonocky,”Optimal Supply and Threshold Scaling for Sub threshold CMOS Circuits “, Proc. Of IEEE Computer Society Annual Symposium on VLSI, 2002, pp. 5-9
R.Shalem, E. John and L. K . John, “A novel low power energy recovery full adder cell”, Proc. Of the IEEE Great Lakes Symposium of VLSI, Feb. 1999, pp. 380-383.
Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and JinGyun Chung, “A Novel Multiplexer-Based Low-Power Full Adder”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 51, No. 7, JULY 2004, PP. 345-348.
H. T. Bui, A. K. Al-Sheraidah, and Y. Wang, “Design and analysis of 10-transistor full adders using novel XOR-XNOR gates,” Proc. Of Int.Conf. on Signal Processing (Wood Computer Congress), Beijing, China, Aug. 2000.
Y. Jiang, Y.Wang, and J.Wu, “Comprehensive power Evaluation of Full Adders,” Florida Atlantic Univ., BocaRaton, Tech. Rep., 2000.
P. M. Lee, C.H. Hsu, and Y. H. Hung, “ Novel 10-T full adders realized by GDI structure”, Proc. on Intl. Symposium on Integrated Circuits (ISIC 2007), pp.
Abu-Shama, M.A. Bayoumi, “A new cell for low poweradders,” Proc. lot. Midwest Symp. Circuits & Systems, pp.1014-1017, 1995.
A.A. Fayed, M.A. Bayoumi, “A Low Power 10-Transistor Full Adder Cell for Embedded Architectures,” Proc. IEEE Symp. Circuits & Systems, Vol. 4, pp. 226- 229, Sydney,Australia, May 2001.
D. Radhakrishnan, “Low-voltage low-power CMOS fulladder,” Proc. Inst. Elect. Eng., Circuits Devices Systems, Vol. 148, No. 1, pp. 19–24, 2001.
O. Kavehie, K. Navi, “A Novel 54×54-bit ScalableMultiplier Architecture,” 13th Iranian Conference onElectrical Engineering, pp. 367-371, May 2005.
C. Chang, J. Gu, M. Zhang, “Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for FastArithmetic Circuits,” IEEE Transactions on Circuits &Systems, Vol. 51, No. 10, pp. 1985-1997, Oct. 2004.
K. Navi, A. Kazeminejad, D. Etiemble, “Performance ofCMOS Current Mode Full Adders”, IEEE Proc. Int‟l. Symp. Multiple Valued Logic, pp. 27-34, May 1994
Refbacks
- There are currently no refbacks.
This work is licensed under a Creative Commons Attribution 3.0 License.