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An Architectural Framework for Power Performance Tuning

I. Flavia Princess Nesamani, J. Kanaka Deva Princy, K. Mariya Priyadarshini, V. Lakshmi Prabha

Abstract


As device and interconnect dimensions continue to shrink and wafer sizes increase, maintaining process uniformity is increasing in importance. An understanding of variation is essential to control the process and to design manufacturable high-performance circuits. In this paper, a low-cost architectural framework for power performance testing and tuning is developed. It brings the delay and power consumption of a die within the acceptable range. Tuning “knobs” such as tunable gates are employed to deal with delay and power variations. This tuning technique improves the delay yield considerably with minimal impact on area.

Keywords


Control Logic, Low Power VLSI, Mentor Graphics, Tunable Gate

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References


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