Timing Optimization Techniques for 90nm Networking Chip

Abstract

In this Paper, Timing Optimization Techniques for Deep Sub-Micron (DSM) Design at Back-end (in Physical Design) is discussed. Because as we Know With Progress. In VLSI Sub-Micron Technology, Overall Complexity Of The Chip Has Increase Dramatically. There Is A Simultaneous Need For More Function And Higher Speed In Modern VLSI Engineering Time Become A Major Issue Therefore, Use Of A Minimum Amount Of Extra Hardware To Meet Timing Requirements Is Becoming A Major Issue In VLSI Design. So here I present some techniques that can Solve all Timing Violations like By using Interface Logic Model (ILM) with this we can also Reduce Run-Time of PD steps By Gate Resizing and Critical Path Identification using -PODEM Algorithm [6], By Net Ordering and wire Optimization [11], By More popular way Buffer Insertion at High Fan-out Node to Reduce Transition Time with Accurate Delay Model(ADM) [16], .By Replacing Flip-Flops to Latches and also some techniques that we can apply only Latch based Design, By an Improved Redundancy Addition and Removal Technique [14], By Pipeline in Critical Path to reduce Delay So These are all about How can Reduce Slack [2].