A Low Power Analysis for SRAM using 6T and 8T Bit Cells

Abstract

The area and power consumption of the SOC devices, occupied by static random access memory (SRAM), increase largely with technology scaling. Thus they are critical components in both high-performance processors and hand-held applications. As a result, SRAM energy power becomes a major issue, and low power SRAM designs, without compromising speed performance, are especially crucial in modern very-large-scale integration (VLSI) designs. Random -access memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-end workstation and microprocessor applications. The heart of an SRAM is the cell array where the data is stored. The memory cell array usually consists of thousand of memory cells depending on the number of bits it can store (word size). The architecture combines built-in self-test and digitally controlled delay elements to reduce the word line pulse width for memories while ensuring correct read operations, hence reducing the switching power. The architecture uses 6T SRAM cell and 8T SRAM cells respectively and the power and area analysis is made accordingly.