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A Novel VLSI Architecture with Reduced Hard Multiple based on Higher Radix Hybrid Modified Booth Algorithm

V. Priyadarshini, C. Rajasekaren, M. Jithin Kumar

Abstract


Hard multiple is the holdup process in higher radix Booth encoded multipliers. In this paper, a High-Level Design approach for the reduction of higher radix hard multiples is proposed. The method is used to optimize and re-design the internal algorithm and architecture of a low power multiplier with high-level design techniques. It can be achieved by a low-power Hybrid Multiplier using Modified Booth Encoder (MBE) by altering its basic Encoding scheme. In this Hybrid technique, Radix-4 (3-Bit) recoding and Radix-8 (4-Bit) encoding schemes are included in Radix-16 (5-Bit) recoding scheme. Synthesis results based on SDK 90nm, 1.32V CMOS standard-cell library shows that the proposed Hybrid multiplier reduces the power consumption by 20-25%.

Keywords


High Level Design, Higher Radix, Modified Booth Encoder, Hard Multiples

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References


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