Robust Fault Secure Data Transmission System for Nanomemory Applications

Abstract

Memory cells and supporting circuitry (encoder & decoder) have been protected from transient errors for more than a decade. Due to the increase in the transient error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to transient errors as well and must also be protected .We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. We introduce a nanowire-based, sublithographic memory architecture tolerant to transient faults. The key novel contribution of this project is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. Both the storage elements and the supporting encoder and corrector are implemented in dense, nanowire based technology. We further quantify the importance of protecting encoder and decoder circuitry against transient errors. We explore scrubbing designs and show the overhead for serial error correction and periodic data scrubbing. We prove that Hamming codes have the fault-secure detector capability. Using some of the smaller Hamming codes, we can tolerate nanowire defect rates with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger Hamming codes can achieve even higher reliability. We present a design which describes the error-correction coding and circuitry used for permanent defect and transient fault tolerance with the help of VHDL modeling.